How to Delay a Pulse Again

Contamination Delay

Static Circuits

David Harris , in Skew-Tolerant Excursion Blueprint, 2001

2.2.4 Min-Delay

And so far, we have focused on the question of max-filibuster: how long the cycle must be for each retention element to meet its setup fourth dimension. The max-delay constraints set the performance of the arrangement, just are relatively innocuous because if they are violated, the circuit can all the same be made to function correctly past reducing the clock frequency. In contrast, circuits likewise have min-filibuster constraints that retentiveness element inputs must not alter until a hold time afterward the sampling edge. If these constraints are violated, the circuit may sample the output while it is changing, leading to incorrect results. Min-delay violations are specially insidious considering they cannot be fixed by changing the clock frequency. Therefore, the designer is forced to be conservative.

Figure 2.six shows how min-delay problems tin lead to incorrect functioning of flip-flops. In the example, in that location are two back-to-back flip-flops with no logic betwixt them. This is common in pipelined circuits where information such as an instruction opcode is carried from one pipeline stage to the next without modification as the pedagogy is processed. Suppose data input D ₁ is valid for a setup and hold time effectually the rising edge of clk, but that the propagation delay to Q _one is especially short. Q ₁ is the input to the second flip-flop and changes before the end of the hold time for the 2d flip-flop. Therefore, the second flip-flop may incorrectly sample this new information and pass it on to Q ₂. In summary, the data that was at input D ₁ before the clock border arrives at not only Q ₁ but also Q _two after the clock border. This is referred to as double-clocking, a hold fourth dimension or min-filibuster violation, or a race.

Figure 2.6. Min-delay problems in flip-flops

The term "min-filibuster" comes from the fact that the problem can exist avoided by guaranteeing a minimum corporeality of delay betwixt consecutive flip-flops. If there were more than delay between the ascent edge of the clock and the fourth dimension data arrived at the second flip-flop, the hold fourth dimension would not take been violated and the excursion would have worked correctly.

Min-delay issues are exacerbated past clock skew. If skew causes the clock of the showtime flip-flop to rise early on, its output volition become valid early. If skew then besides causes the clock of the 2d flip-flop to rise belatedly, its input will have to hold until a later time. Therefore, more than delay is necessary betwixt the flip-flops to ensure the concord time is not violated. Clock skew tin be viewed as increasing the effective hold time of the second memory element.

Nosotros can guarantee that min-delay problems will never occur past checking a uncomplicated delay constraint between each pair of consecutive retentivity elements. Assume that information departs the get-go element every bit early as possible. Add the shortest possible delay between this departure time and the arrival at the second element; this is called the contamination delay. The arrival must be at least a concord time after the sampling edge of the second chemical element, bold maximum skew between the elements. To analyze our prospective latching techniques, we need a few more definitions. Allow the states define δ _cq as the contagion delay of the retentiveness element, that is, the minimum time from the clock switching until the output becoming valid. This is like δ _CQ only represents the minimum instead of maximum delay. Permit δ_logic be the contamination delay through the logic between the memory elements.

For flip-flops, data departs the first flip-flop on the rise edge of the clock. The bomb and logic contamination delays must be adequate for the data to go far at the 2d flip-flop after its hold fourth dimension has elapsed, even budgeting clock skew:

(ii.7) ${\delta }_{CQ}+{\delta }_{\text{logic}}\ge {\Delta }_{CD}+t_{\text{skew}}$

Solving for the minimum logic contamination delay, we find

(2.viii) ${\delta }_{\text{logic}}\ge {\Delta }_{CD}+t_{\text{skew}}-{\delta }_{CQ}$

Notice that the constraint is independent of cycle time T_c. Every bit expected, min-delay problems cannot be fixed by adjusting the cycle time.

For latches, data departs the kickoff latch on the rise edge of one half-bicycle. The latch and logic contamination delays must be sufficient for the information to make it a hold fourth dimension after the falling edge of the previous half-cycle.

Let united states of america define t _nonoverlap as the fourth dimension from the falling edge of one one-half-cycle to the rise border of the adjacent. This time is typically 0 for complementary clocks, just may exist positive for nonoverlapping clocks. The minimum logic contamination filibuster is

(2.9) ${\delta }_{\text{logic}}\ge {\Delta }_{CD}+t_{\text{skew}}-{\delta }_{CQ}-t_{\text{nonoverlap}}$

Notice that this minimum filibuster is through each half-cycle of logic. Therefore the full cycle requires minimum delay twice equally great.

The following example may analyze the use of nonoverlapping clocks:

Example ii.1

What is the logic contamination delay required in a system using transparent latches if the hold fourth dimension is 0, the latch contamination delay is 0.5 FO4 inverter delays, the clock skew is i FO4 delay, and the nonoverlap is ii FO4 delays, equally shown in Figure 2.7?

Figure ii.7. Transparent latches with nonoverlapping clocks

SOLUTION

δ_logic must exist at least 0 + 1 – 0.5 – two = −1.5 FO4 delays. Considering logic delays are ever nonnegative, it is incommunicable for this organisation to experience min-delay problems.

2-phase nonoverlapping clocking was once popular considering of min-filibuster prophylactic. It is still a skillful choice for educatee projects because it is completely rubber; by using external command of the clock waveforms, the student can always provide plenty nonoverlap and boring-enough clocks to avoid problems with either min-delay or max-delay. However, commercial loftier-speed designs seldom use nonoverlapping clocks considering it is easier to distribute a unmarried clock globally, and and so locally capsize it to obtain the ii latch phases. Instead, the commercial designs bank check min-delay and insert buffers to increase delay in fast paths. Nonoverlapping clocks too reduce the possible amount of time borrowing. Note that at that place is a common fallacy that nonoverlapping clocks allow less fourth dimension for useful computation. As tin can be seen from Figure 2.7, this is not the case; the full bike less 2 latch delays is still available. The just penalization is the reduced opportunity for time borrowing.

For pulsed latches, data departs the kickoff latch on the rising edge of the pulse. Information technology must not arrive at the second pulsed latch until a concord fourth dimension after the falling edge of the pulse. Every bit usual, the presence of clock skews between the pulses increases the hold fourth dimension. Therefore, the minimum contamination delay is

(2.10) ${\delta }_{\text{logic}}\ge t_{pw}+{\Delta }_{CD}+t_{\text{skew}}-{\delta }_{CQ}$

This is the largest required contagion delay of any latching scheme. Information technology shows the trade-off that although wider pulses can hide more than clock skew and even permit small amounts of time borrowing, the wide pulses increase the minimum corporeality of filibuster between latches. Adding this amount of delay between pulsed latches in cycles that perform no logic tin can take a significant corporeality of surface area. Therefore, systems that use pulsed latches for the critical paths that crave low sequencing overhead sometimes also utilize flip-flops to reduce min-delay problems on paths that merely stage data along without processing.

Y'all may have noticed that flip-flops and pulsed latches have a minimum delay per cycle, while transparent latches accept a minimum delay per half-cycle, and hence virtually twice every bit much minimum filibuster per cycle. This may seem strange because flip-flops can be built from a pair of dorsum-to-dorsum transparent latches. Why should flip-flops have half the min-filibuster requirement equally transparent latches if the systems have exactly the aforementioned building blocks? The answer is that flip-flops are commonly constructed with aught skew between adjacent latches. By making the concord time Δ _CD less than the contamination delay δ _DQ, the minimum logic filibuster betwixt the two latches in the flip-bomb is negative. If this were not the case, flip-flops would insidiously neglect by sampling the input on the falling edge of the clock as well as the ascent edge! We will revisit this outcome while discussing flip-flop design in Section two.iii.three.

Min-filibuster can be enforced in many brusque paths by adding buffers. Long channel lengths are ofttimes used to make slower buffers and so that fewer buffers are required. The hardest min-filibuster issues occur in paths that could exist either fast or ho-hum in a information-dependent fashion. For instance, a path built from a serial of nand gates may be fast when both parallel pmos transistors plough on and slower when only one pmos transistor turns on. A path using wide domino or gates is even more than sensitive to input patterns. Therefore, circuit designers occasionally encounter paths that have both min- and max-delay issues. Because buffers cannot be added without exacerbating the max-filibuster problem, the circuits may have to be redesigned.

Min-delay requirements are piece of cake to check because they merely involve delays between pairs of sequent retention elements. They are also conservative for systems that permit time borrowing because they assume data ever departs the commencement latch at the earliest possible time. In a real organisation, time borrowing may cause data to depart the showtime latch somewhat later, making min-filibuster easier to satisfy. Unfortunately, if the existent system is operated at reduced frequency, or at higher voltage where transistors are faster, information may again depart the first latch at the primeval possible time. Therefore, it is unwise to depend on data departing late to guarantee min-delay.

Because min-filibuster violations result in nonfunctional circuits at whatsoever operating frequency, it is necessary to be conservative when checking and guaranteeing hold times. Discovering min-filibuster problems afterward receiving chips back from fabrication is extremely expensive because the violation must be fixed and new chips must exist built before the debugging of other problems such as long paths or logic errors can brainstorm. This may add two to four months to the debug schedule in an industry with production cycles of two years or less.

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Combinational Logic Design

Sarah Fifty. Harris , David Harris , in Digital Design and Computer Architecture, 2022

2.nine.ane Propagation and Contamination Delay

Combinational logic is characterized by its propagation delay and contagion delay . The propagation delay t _pd is the maximum time from when any input changes until the output or outputs reach their final value. The contagion delay t _cd is the minimum time from when any input changes until any output starts to modify its value.

When designers speak of calculating the delay of a circuit, they generally are referring to the worst-instance value (the propagation delay), unless information technology is articulate otherwise from the context.

Figure 2.67 illustrates a buffer's propagation filibuster and contagion delay in blue and greyness, respectively. The effigy shows that A is initially either High or LOW and changes to the other land at a detail time; we are interested only in the fact that it changes, non what value information technology has. In response, Y changes some time later. The arcs bespeak that Y may start to modify t _cd afterward A transitions and that Y definitely settles to its new value within t _pd .

Figure 2.67. Propagation and contamination filibuster

The underlying causes of filibuster in circuits include the time required to accuse the capacitance in a circuit and the speed of light. t _pd and t _cd may be different for many reasons, including

▸

different rising and falling delays

▸

multiple inputs and outputs, some of which are faster than others

▸

circuits slowing downwardly when hot and speeding upwardly when common cold

Calculating t _pd and t _cd requires delving into the lower levels of brainchild beyond the scope of this book. Nevertheless, manufacturers normally supply data sheets specifying these delays for each gate.

Circuit delays are normally on the society of picoseconds (1   ps = 10⁻¹² seconds) to nanoseconds (1   ns = 10^−ix seconds). Trillions of picoseconds take elapsed in the time yous spent reading this sidebar.

Along with the factors already listed, propagation and contamination delays are likewise determined by the path a point takes from input to output. Figure 2.68 shows a four-input logic circuit. The critical path, shown in blue, is the path from input A or B to output Y. It is the longest—and, therefore, the slowest—path because the input travels through three gates to the output. This path is critical because it limits the speed at which the circuit operates. The curt path through the excursion, shown in grey, is from input D to output Y. This is the shortest—and, therefore, the fastest—path through the circuit because the input travels through but a unmarried gate to the output.

Figure 2.68. Short path and critical path

The propagation delay of a combinational circuit is the sum of the propagation delays through each element on the critical path. The contamination filibuster is the sum of the contagion delays through each chemical element on the short path. These delays are illustrated in Figure two.69 and are described past the following equations:

Figure 2.69. Critical and short path waveforms

Although we are ignoring wire delay in this analysis, digital circuits are now and so fast that the delay of long wires tin can exist as important as the delay of the gates. The speed of light filibuster in wires is covered in Appendix A.

(two.8) $t_{pd}=2t_{p{d}_{\_}\mathrm{AND}}+t_{p{d}_{\_}\mathrm{OR}}$

(2.9) $t_{cd}=t_{c{d}_{\_}\mathrm{AND}}$

Example two.15

Finding Delays

Ben Bitdiddle needs to find the propagation delay and contamination delay of the circuit shown in Figure 2.lxx. According to his data book, each gate has a propagation delay of 100 picoseconds (ps) and a contamination delay of sixty   ps.

Figure two.70. Ben's circuit

Solution

Ben begins by finding the critical path and the shortest path through the circuit. The critical path, highlighted in bluish in Figure 2.71, is from input A or B through three gates to the output Y. Hence, t _pd is three times the propagation filibuster of a unmarried gate, or 300   ps.

Figure ii.71. Ben's critical path

The shortest path, shown in grayness in Figure ii.72, is from input C, D, or East through two gates to the output Y. There are only two gates in the shortest path, and then t _cd is 120   ps.

Figure ii.72. Ben's shortest path

Case 2.xvi

Multiplexer Timing: Control-Critical VS. Information-Critical

Compare the worst-case timing of the three four-input multiplexer designs shown in Figure 2.58 on page 83. Table 2.7 lists the propagation delays for the components. What is the critical path for each design? Given your timing analysis, why might yous choose one design over the other?

Table 2.seven. Timing specifications for multiplexer excursion elements

Gate	t pd (ps)
Non	xxx
ii-input AND	60
iii-input AND	80
four-input OR	ninety
tristate (A to Y)	50
tristate (enable to Y)	35

Solution

One of the critical paths for each of the three blueprint options is highlighted in blue in Figures 2.73 and 2.74. t _{pd_sy} indicates the propagation delay from input Due south to output Y; t _{pd_dy} indicates the propagation filibuster from input D to output Y; t _pd for the excursion is the worst of the two: max(t _{pd_sy} , t _{pd_dy} ).

Effigy 2.73. iv:1 multiplexer propagation delays: (a) two-level logic, (b) tristate

Effigy ii.74. 4:one multiplexer propagation delays: hierarchical using 2:1 multiplexers

For both the two-level logic and tristate implementations in Effigy 2.73, the critical path is from one of the control signals Southward to the output Y: t _pd = t _{pd_sy} . These circuits are control critical, because the critical path is from the control signals to the output. Any boosted delay in the control signals will add direct to the worst-case filibuster. The delay from D to Y in Figure ii.73(b) is merely fifty   ps, compared with the delay from S to Y of 125   ps.

Figure two.74 shows the hierarchical implementation of the 4:ane multiplexer using two stages of 2:1 multiplexers. The critical path is from any of the D inputs to the output. This circuit is information critical, because the critical path is from the data input to the output: t _pd = t _{pd_dy} .

If information inputs arrive well before the control inputs, nosotros would prefer the pattern with the shortest control-to-output delay (the hierarchical design in Figure 2.74). Similarly, if the command inputs go far well before the data inputs, we would adopt the blueprint with the shortest data-to-output delay (the tristate design in Figure 2.73(b)).

The best choice depends not only on the critical path through the circuit and the input arrival times but also on the ability, cost, and availability of parts.

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Excursion Modeling with Hardware Clarification Languages

In Summit-Down Digital VLSI Design, 2015

Delay modeling

In the context of simulation, the lapse of time between an update effect at the input of a procedure and the ensuing event scheduled at the output reflects the delay of the piece of hardware being modeled. Circuit delays are typically conveyed by a # expression which forms an optional office of the various consignment statements. The continuous assignment beneath, for instance, models the propagation delay of an adder by scheduling an update event on its output t _pd subsequently an issue at either input.

Example                                                                                           assign #TPD Oup_D = InpA_D + InpB_D;

The adjacent simulation model uses a procedural cake to also account for contamination delay t _cd .

always_comb

begin

  Oup_D <= #TCD ′{default:1′bX}; // revert all $.25 to unknown afterward tcd

  Oup_D <= #TPD InpA_D + InpB_D; // propagate issue to output after tpd end

Hint: SystemVerilog accepts time values in multiples of some time unit previously divers with a timeunit statement or a 'timescale compiler directive, eastward.thou. #two.8. To avert surprises, always specify the measurement unit, i.e. write #2.8ns instead.

Hint: When simulating models with zero delays it becomes difficult to tell autonomously cause and issue in the output waveforms as the respective update events announced to coincide. A play tricks is to artificially postpone future events by a tiny amount of fourth dimension in otherwise delayless variable assignments. To allow for quick adjustments, a abiding is all-time declared in a package and referenced throughout a model bureaucracy. Annotation that the largest sum of fake delays must not exceed one clock period, though.

Instance assign #FAKEDELAY Oup_D = InpA_D + InpB_D;

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Conquering of Asynchronous Information

In Top-Downwards Digital VLSI Design, 2015

8.iii.1 No synchronization whatsoever

In the excursion of fig.8.9a, a scalar input betoken Data is being fed into ii combinational subcircuits k and h that are part of a synchronous consumer excursion without any prior synchronization to the local clock ClkQ. Ii deficiencies are likely to pb to system failure.

Figure 8.9. Acquisition of scalar inputs (irrelevant details not shown). No synchronization (a), synchronization at multiple places (b), and synchronization at a single place with inadequate (c), and with adequate sampling rate (d) (recommended).

Firstly, signals Grand and H emanating from g and h respectively volition occasionally become sampled during the time span between contagion and propagation delay when their values correspond neither to the settled values from the past interval t nor to those for the upcoming interval t + 1. ¹⁰ In the timing diagram of fig.8.9a such unfortunate circumstances employ to the central clock upshot.

Secondly, even though G and H may happen to be stable at sampling time, they may chronicle to distinct time intervals if t _{cd g} > t _{pd h} . If then, an inconsistent set of data gets stored in the two registers before beingness passed on to the downstream circuitry for farther processing. This undesirable state of affairs typically occurs when i of the paths includes combinational logic whereas the other does not. For an example, cheque the rightmost clock effect in fig.8.9a.

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Clocking of Synchronous Circuits

In Pinnacle-Down Digital VLSI Design, 2015

Example

Table 7.2 is an excerpt from the datasheet of a CMOS flip-bomb. ^vi The maximum admissible clock skew between any two such flip-flops where the Q output of one cell directly connects to the D input of the next is 124   ps   −   (−   14   ps)   =   138   ps. Please keep in mind this is just an estimate that assumes identical MOSFETs and PTV conditions throughout. The beneficial impact of interconnect filibuster is also ignored, on the other mitt.

Observation 7.4

Matching of clock distribution delays and conscientious timing analysis are disquisitional when designing circuits and systems with edge-triggered ane-phase clocking. Shift registers and scan paths are particularly vulnerable to (positive) clock skew.

Table 7.two. Timing characteristics of a standard cell flip-flop in a 130   nm CMOS engineering science.

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Sequential Logic Design

Sarah L. Harris , David Money Harris , in Digital Design and Computer Architecture, 2016

Putting It All Together

Sequential circuits accept setup and concur time constraints that dictate the maximum and minimum delays of the combinational logic betwixt flip-flops. Modernistic flip-flops are usually designed and then that the minimum delay through the combinational logic is 0—that is, flip-flops can exist placed back-to-back. The maximum delay constraint limits the number of consecutive gates on the critical path of a high-speed circuit, because a loftier clock frequency means a brusk clock period.

Example three.10

Timing Analysis

Ben Bitdiddle designed the circuit in Figure 3.42. According to the information sheets for the components he is using, flip-flops have a clock-to-Q contamination delay of 30  ps and a propagation delay of 80   ps. They have a setup time of l   ps and a hold time of 60   ps. Each logic gate has a propagation delay of twoscore   ps and a contamination delay of 25   ps. Help Ben decide the maximum clock frequency and whether any hold fourth dimension violations could occur. This process is called timing assay.

Figure 3.42. Sample circuit for timing analysis

Solution

Figure three.43(a) shows waveforms illustrating when the signals might alter. The inputs, A to D, are registered, so they only change shortly subsequently CLK rises.

Effigy 3.43. Timing diagram: (a) general case, (b) critical path, (c) short path

The critical path occurs when B = i, C = 0, D = 0, and A rises from 0 to 1, triggering n1 to ascension, X′ to rise, and Y′ to fall, every bit shown in Figure 3.43(b). This path involves three gate delays. For the critical path, nosotros assume that each gate requires its full propagation delay. Y′ must setup before the side by side rising edge of the CLK. Hence, the minimum wheel time is

(3.18) $T_c\ge t_{pcq}+3t_{pd}+t_{\text{setup}}=80+3\times 40+50=250\text{\hspace{0.17em}ps}$

The maximum clock frequency is f_c = 1/T_c = four   GHz.

A short path occurs when A = 0 and C rises, causing X′ to ascension, as shown in Figure iii.43(c) . For the short path, nosotros assume that each gate switches after only a contamination delay. This path involves only 1 gate delay, so it may occur later on t_ccq + t_cd = 30 + 25 = 55   ps. But recall that the flip-bomb has a hold time of threescore   ps, significant that X′ must remain stable for sixty   ps afterwards the rising edge of CLK for the flip-flop to reliably sample its value. In this example, 10′ = 0 at the outset rising edge of CLK, so we want the flip-flop to capture X = 0. Because Ten′ did not hold stable long plenty, the actual value of X is unpredictable. The circuit has a concord fourth dimension violation and may behave erratically at any clock frequency.

Instance 3.11

Fixing Hold Time Violations

Alyssa P. Hacker proposes to fix Ben's circuit by calculation buffers to slow down the short paths, as shown in Figure 3.44. The buffers have the aforementioned delays as other gates. Help her decide the maximum clock frequency and whether whatever hold time bug could occur.

Effigy iii.44. Corrected excursion to fix hold fourth dimension problem

Solution

Effigy 3.45 shows waveforms illustrating when the signals might change. The critical path from A to Y is unaffected, because information technology does not pass through any buffers. Therefore, the maximum clock frequency is still 4 GHz. Withal, the short paths are slowed by the contagion delay of the buffer. Now X′ will non modify until t_ccq + 2t_cd = xxx + ii × 25 = 80   ps. This is afterward the 60   ps hold time has elapsed, then the excursion at present operates correctly.

Effigy 3.45. Timing diagram with buffers to prepare hold time problem

This example had an unusually long concord time to illustrate the bespeak of hold time problems. Most flip-flops are designed with t _hold < t_ccq to avert such bug. However, some high-functioning microprocessors, including the Pentium 4, utilize an element chosen a pulsed latch in place of a flip-bomb. The pulsed latch behaves similar a flip-flop merely has a short clock-to-Q filibuster and a long hold time. In general, adding buffers tin ordinarily, just non always, solve hold time issues without slowing the critical path.

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Sequential Logic Blueprint

Sarah L. Harris , David Harris , in Digital Design and Figurer Architecture, 2022

Concord Time Constraint

The register R2 in Figure 3.38(a) as well has a hold time constraint. Its input, Dtwo, must not change until some time, t _concord, after the rising border of the clock. According to Figure 3.40, D2 might change as shortly as t _ccq + t _cd after the rise edge of the clock. Hence, we detect

Effigy 3.40. Minimum delay for hold time constraint

(three.xv) $t_{\mathit{ccq}}+t_{\mathit{cd}}\ge t_{\text{hold}}$

Once again, t _ccq and t _hold are characteristics of the flip-flop that are usually exterior the designer's command. Rearranging, we can solve for the minimum contagion delay through the combinational logic:

(three.16) $t_{\mathit{cd}}\ge t_{\text{hold}}-t_{\mathit{ccq}}$

Equation 3.16 is called the hold time constraint or min-filibuster constraint because information technology limits the minimum delay through combinational logic.

Nosotros have causeless that any logic elements can exist connected to each other without introducing timing problems. In detail, we would expect that two flip-flops may exist directly cascaded as in Figure 3.41 without causing concur fourth dimension issues.

Effigy 3.41. Back-to-back flip-flops

In such a instance, t _cd = 0 because there is no combinational logic between flip-flops. Substituting into Equation three.sixteen yields the requirement that

(3.17) $t_{\text{hold}}\le t_{\mathit{ccq}}$

In other words, a reliable flip-flop must take a agree fourth dimension shorter than its contamination delay. Often, flip-flops are designed with t _hold = 0 so that Equation three.17 is e'er satisfied. Unless noted otherwise, we will ordinarily brand that assumption and ignore the hold time constraint in this book.

Notwithstanding, hold fourth dimension constraints are critically of import. If they are violated, the only solution is to increment the contamination delay through the logic, which requires redesigning the excursion. Unlike setup time constraints, they cannot be fixed past adjusting the clock period. Redesigning an integrated circuit and manufacturing the corrected design takes months and millions of dollars in today'south advanced technologies, so hold time violations must be taken extremely seriously.

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The Case For Synchronous Design

In Top-Down Digital VLSI Design, 2015

6.3.ii The pros and cons of synchronous clocking

There are ten essential benefits that are shared past all synchronous clocking disciplines.

+

Hazards do not compromise functionality. Clock and asynchronous reset are the only two signals that must be kept free of hazards under all circumstances. Doing and then is like shooting fish in a barrel, strictly limiting distribution networks to fanout trees suffices.

+

As no timing violations always occur within a properly designed synchronous circuit, there is no chance for inconsistent information, marginal triggering, and metastability to develop.

+

Immunity to noise and coupling effects is maximum because all nodes are immune to settle before any storage operations and country changes occur.

+

All timing constraints are one-sided. For a circuit to role correctly, any timing quantity is either divisional from above (such as the longest propagation delay, for instance) or from below (such as the contamination delays). Ii-sided constraints do not be. ⁹

+

Together, the to a higher place four properties warrant deterministic behavior of circuits independently from low-level details. ¹⁰ Synchronous designs do not rely on delay tuning in any way. What matters for functional definiteness are the data operations at the RTL level exclusively. This argument cannot exist overestimated in view of

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Automated placement, routing, and physical design verification,

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Automatic HDL synthesis, logic optimization, clock tree generation, and rebuffering,

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Automatic insertion of test structures,

•

Reusing a HDL model or a netlist in multiple designs, and of

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Retargeting a design from one jail cell library and/or fabrication procedure to another (east.g. from FPL to a mask-programmed IC, or vice versa).

+

Synchronous functioning makes information technology possible to separate functional verification from timing analysis and to take advantage of automata theory and related concepts.

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There is no need for any redundant circuitry to suppress hazards, a task not supported by standard synthesis tools.

+

The compute operations that are to exist carried out in each clock bicycle can be stated and collected at compile time, thereby opening a door for bicycle-based simulation techniques that are more than efficient when circuits grow large. Asynchronous circuits, in contrast, are entirely dependent on consequence-driven simulation.

+

Established methods for excursion testing (such as fault grading, test vector generation, and the insertion of test structures) start from the assumption of synchronous performance. What'south more, well-nigh all exam equipment is designed accordingly.

+

Synchronous clocking makes it possible to slow downward and fifty-fifty to suspend circuit performance in any state and for an arbitrary lapse of fourth dimension, ^eleven which greatly facilitates the tracing of country transitions, data transfers, protocol sequences, and computation flow when debugging a malfunctioning circuit. The capability to operate synchronous circuits in speed-limited environments is ofttimes welcome for prototyping purposes.

Undeniably, synchronous circuit performance besides has its drawbacks.

−

Performance is determined by the worst rather than by the average filibuster over all information. ¹²

−

Circuits may swallow more power than necessary equally a register dissipates energy in each clock wheel regardless of the extent of country change. Yet, clock gating and other techniques take been developed specifically to lower clock-induced power dissipation while maintaining overall synchronous excursion operation.

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Synchronous operation causes periodic surges in supply currents. This not only strains the power and footing nets but besides entails electromagnetic radiation at the clock frequency and at higher harmonics.

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Synchronization problems are unavoidable at the interface between whatsoever two clock domains. ¹³ Yet, similar problems arise wherever an asynchronous subsystem interfaces with a clock-driven surroundings such as a sampled data source or information sink.

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Virtually synchronous clocking disciplines insist on tightly controlled delays within the clock distribution network. Special software tools that address this need during concrete design make role of all major VLSI CAD suites.

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Domino Circuits

David Harris , in Skew-Tolerant Excursion Pattern, 2001

3.five Exercises

[fifteen] 3.one

Sketch a diagram like Figure 3.i illustrating a half dozen-phase domino pipeline with 50% duty cycle clocks and one domino gate per clock phase. Indicate clock skew of one-sixth of the cycle.

[15] 3.2

A domino gate has an evaluation fourth dimension of 100 ps and a precharge fourth dimension of 200 ps. If there is l ps of skew between the clock controlling the gate and its successors in the same phase, what is the minimum time t_p that the clock must be depression?

[20] 3.3

Repeat Example 3.1 if the cycle fourth dimension is 12 FO4 delays and the precharge time is 3 FO4 delays.

[20] 3.four

Repeat Example 3.ii if the bike time is 12 FO4 delays and the precharge fourth dimension is 3 FO4 delays.

[15] 3.5

A four-stage skew-tolerant domino pipeline runs at 800 MHz in a 0.18-micron procedure with a threescore ps FO4 filibuster. You tin can conform the duty wheel of the clocks for best performance. If you lot allow a precharge time of 5 FO4 delays and a agree time of one FO4 delay, when at that place is 50 ps of local clock skew, how much global skew can you tolerate? If the actual global skew is 200 ps, how much time borrowing tin can you allow?

[xxx] 3.6

Repeat Exercise 3.5 if y'all design to guarantee exactly one domino gate per clock stage.

[xx] 3.seven

A four-phase skew-tolerant domino pipeline runs at 1.25 GHz using 50% duty cycle clocks. The required overlap between phases is t _concur = −15 ps. Each domino gate has a contagion delay of 35 ps and a hold fourth dimension Δ _cd of −10 ps. How much clock skew tin the pipeline withstand before one gate might precharge before its successor could eat the event? How much clock skew can the pipeline withstand before min-filibuster issues might occur? In summary, how much clock skew tin can the system withstand?

[20] 3.eight

Sketch transistor-level implementations of the following footed dual-rail dynamic gates:

(a)

OR/NOR

(b)

AND-OR-INVERT (AOI)

(c)

three-input MAJORITY (output TRUE if at least 2 inputs are Truthful)

(d)

three-input XOR

[20] 3.9

Sketch transistor-level implementations of the post-obit footed dynamic gates. Label each nmos transistor with the appropriate width to provide the same output bulldoze as a unit inverter (see Figure 3.11). Select the pmos transistor width for half the output drive equally the pulldown stack. Estimate the logical endeavor of each data input to the gate.

(a)

NAND2

(b)

NAND3

(c)

NOR2

(d)

NOR3

(e)

AND-OR-INVERT (AOI)

[xv] 3.ten

Repeat Practise 3.ix for unfooted dynamic gates.

[30] iii.xi

Brand plots of evaluation time and precharge time for the domino buffer in Figure 3.24 as a function of the precharge transistor size P. The transistor and load sizes have been selected to provide a stage effort of about four. Utilize stride inputs. Measure out evaluation time to l% output of the static inverter when Φ is already loftier and A rises. Measure precharge time from the falling edge of Φ to the static inverter output Y dropping to x% of V_DD. Utilize your favorite process, environment, and SPICE simulator. Let the dimensions be in units of 10 microns of gate width. What value of P would you select for general application?

Figure 3.24. Domino buffer for simulation of precharge transistor size

[xxx] 3.12

Make plots of evaluation fourth dimension and input noise margin for the domino buffer in Figure 3.25 as a function of the keeper transistor size k. Utilize step inputs. Measure evaluation time to l% output of the static inverter when Φ is already high and A rises. Measure out noise margin at the unity gain point of the output Y. Employ your favorite process, environment, and SPICE simulator. Let the dimensions be in units of 10 microns of gate width. What value of k would y'all select for general application?

Figure 3.25. Domino buffer for simulation of keeper size

[30] 3.xiii

Design a dynamic footed AOAOAOI gate to compute B(C + D(E + F(1000 + H))). Choose the transistor sizes to have a maximum of 20 microns of gate width on whatever input. The gate should bulldoze an inverter with a full of 20h microns of gate width. Simulate it in SPICE, being certain to include AS, AD, PS, and PD parameters to specify diffusion parasitics. Notice the worst-case charge-sharing noise on the output for h = 0, 1, two, 4, and 8. How does the noise depend on h? Why? Add secondary precharge transistors to precharge every other internal node. Repeat your charge-sharing measurements. Explain your observations.

[30] iii.xiv

Simulate capacitive coupling between 2 metal lines. Each line has a capacitance to ground of 0.1 fF/micron and a capacitance to the adjacent line of 0.ii fF/micron. The aggressor's commuter is a falling voltage pace with an constructive resistance of 100 Ω. The victim is a dynamic node; the keeper has an constructive resistance of R. Plot the peak coupling racket versus R for 100-micron and 1 mm line lengths. How do your results compare with the predictions of Equation 3.11?

[25] three.fifteen

Simulate the DC transfer characteristics of an inverter in your procedure, using a P/Northward ratio of 2. Find the unity gain points on the transfer function. Mensurate V _in–l and V _in–h , the input voltages at the low and high unity proceeds points; and V _out–l and 5 _out–h , the output voltages at these points. What are the high and low noise margins for your inverter?

[25] 3.sixteen

Repeat the simulation of Exercise 3.fifteen with a P/N ratio of γ. What value of γ gives equal high and low dissonance margins in your process?

[25] three.17

Identify potential noise issues in the excursion in Figure 3.26. Draw an improved circuit with reduced noise run a risk.

Figure three.26. Noise-prone circuit

[xv] iii.18

An early on stepping of a well-known microprocessor suffered unreliable performance due to racket. The problem was traced to a path between two widely separated units. The receiving unit of measurement used a transmission-gate latch, equally shown in Effigy 3.27(a). The problem could be fixed by substituting a different transparent latch, shown in Figure three.27(b). Explain why the noise problem might occur and how the input noise margins of each latch compare.

Figure iii.27. Path between units with racket problem: inverter after transmission gate (a) and inverter earlier transmission gate (b)

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